Figure 1’s negative constant current source has been a textbook application for the LM337 regulator forever (or thereabouts). It precisely maintains a constant output current (Iout) by forcing the OUTPUT pin to be the negative Vadj relative to the ADJ pin. Thus, Iout = Vadj/Rs.
Figure 1 Classic LM337 constant negative current source where Iout ≃ Vadj/Rs = 1.25/Rs.
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It has worked well for half a century despite its inflexibility. I say it’s inflexible because the way you program Iout is by changing Rs. It may be hard to believe that a part so mature (okay old) as the 337 might have any new tricks left to learn, but Figure 2 teaches it one anyway. It’s a novel topology with better agility. It leaves the resistors constant and instead programs Iout with the (much smaller) control current (Ic).
Figure 2 Rc typically >100Rs, therefore Ic < Iout/100 and Iout ≃ -(1.25 – (IcRc))/Rs.
Rc > 100Rs allows control of current of Iout with only milliamps of Ic. Figure 3 shows the idea fleshed out into a complete PWM-controlled 18 V, 1 A grounded-load negative current source.
Figure 3 An 18 V, 1 A, PWM-programmed grounded load negative current source with a novel LM337 topology. With this topology, accuracy is insensitive to supply rail tolerance. The asterisked resistors are 1% or better and Rs = 1.25 Ω.
The PWM frequency, Fpwm, is assumed to be 10 kHz or thereabouts, if it isn’t, scale C1 and C3 appropriately with:
C1 = 0.5µF*10kHz/Fpwm and,
C3 = 2µF*10kHz/Fpwm.
The resulting 5-Vpp PWM switching by Q1 creates a variable resistance averaged by C1 to R4/Df, where Df = the 0 to 1 PWM duty factor. Thus, at Z1’s Adj point:
Ic = 0 to 1.24V/R4 = 3.1 mA,
The second-order PWM ripple filtering gives a respectable 8-bit settling time of 6 ms with Fpwm = 10 kHz.
Z1 servos the V1 gate drive of Q3 to hold the FET’s source at its precision 1.24-V reference and then level shift the resulting Ic to track U1’s ADJ pin. Also summed with Ic is Iadj bias compensation (1.24V/20k = 62µA) provided by R2.
This term zeros out U1’s typical Iadj and cuts its max 100 µA error by 60%. Meanwhile, D1 insures that Iout is forced to zero when 5 V drops by saturating Q2 and making Ic large enough to turn U1 completely off, thus protecting the load.
About the 1N4001 daisy chain: There’s a possibility of Iout > 0 at Ic = max and a resulting reverse bias of the load; some loads might not tolerate this. The 1N4001s block that, and also provide bias for the power-down cutoff of Iout when +5-V rail shuts down.
Note that the accuracy of IcRc = Vadj is assured by the match of the Rc resistors and precision of the Z1 and U1 internal references. It’s therefore independent of the tolerance of the +5-V rail, although it should be accurate to ± 5% for best PWM ripple suppression. Iout is linear with PWM duty factor Df = 0 to 1:
Iout = -1.25 Df/Rs
If Rs = 1.25 Ω, then Iout(max) = 1 A.
Note that U1 may have to dissipate as much as 23 W if Iout(max) = 1 A and the load voltage is low. Moral of the story: Be generous with the heatsink area! Also, Rs should be rated for a wattage of 1.252/Rs.
Stephen Woodward’s relationship with EDN’s DI column goes back quite a long way. Over 100 submissions have been accepted since his first contribution back in 1974.
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