Chiplets—discrete semiconductor components co-designed and manufactured separately before being integrated into a larger system—are emerging as a groundbreaking approach to addressing many of the challenges faced by monolithic system-on-chip (SoC) designs. They have also become a major venue for increasing transistor density as Moore’s Law slows down.
IDTechEx report “Chiplet Technology 2025-2035: Technology, Opportunities, Applications” asserts that the chiplets approach resembles an SoC on a module, where each chiplet is designed to function in conjunction with others, necessitating co-optimization in design. Moreover, chiplets are increasingly associated with heterogeneous integration and advanced packaging technologies.
While large semiconductor outfits like AMD and Intel were initially prominent in the chiplets world, IP players are now increasingly visible in showcasing the potential of chiplets. That includes established IP players like Arm and Cadence as well as upstarts such as Alphawave Semi.
Cadence’s Arm-based system chiplet
Cadence joined hands with Arm in March 2024 to deliver a chiplet-based reference design, and the outcome of this collaboration is what Cadence calls the industry’s first system chiplet. It integrates processors, system IP, and memory IP within a single package while interconnected through the Universal Chiplet Interconnect Express (UCIe) standard interface.
Figure 1 The system chiplet comprises components such as a system processor, safety management processor, controllers, and PHY IPs for LPDDR5 and UCIe. Source: Cadence
The system chiplet—complying with Arm’s Chiplet System Architecture (CSA)—features of the overall multi-chiplet SoC functionality. It accommodates up to 64 GB/s peak bandwidth for UCIe IP and 32 GB/s peak memory bandwidth for LPDDR5 IP.
AI accelerator chiplet
Another SoC-like emulation on a chiplet platform comes from South Korean AI chip startup Rebellions, which calls its chiplet-based compute accelerator SoC “REBEL. This AI accelerator—designed for generative AI workloads in AI and hyperscale data centers—employs Alphawave Semi’s multiprotocol I/O connectivity chiplets, which integrate PCIe 6.0, CXL 3.1, and Ethernet subsystems with UCIe 2.0 die-to-die connectivity.
Figure 2 The UCIe subsystem serves as the foundation for Rebellions’ REBEL chiplet. Source: Alphawave Semi
It’s another example of a customizable design employing high-speed connectivity and interoperable chiplet architectures. As a result, the chiplet can be deployed as modular building blocks, scalable from single cards to full racks.
The above developments demonstrate how chiplets can help overcome Moore’s Law limits while enhancing function density. Furthermore, they showcase how the chiplets ecosystem allows companies to source different parts from multiple suppliers across various regions.
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