Renesas is sampling a trio of interface ICs for second-generation DDR5 multiplexed rank dual in-line memory modules (MRDIMMs). This complete memory interface chipset includes the RRG50120 multiplexed registered clock driver (MRCD), RRG51020 multiplexed data buffer (MDB), and RRG53220 power management integrated circuit (PMIC).
Gen 2 DDR5 MRDIMMs address the growing memory bandwidth demands of artificial intelligence, high-performance computing, and other data center applications. They deliver operating speeds of up to 10,000 MT/s, with future iterations targeting 12,800 MT/s.
The second-generation RRG50120 MRCD buffers the command/address bus, chip selects, and clocks between the host controller and DRAMs in MRDIMMs. It reduces power consumption by 45% compared to the first generation, improving heat management in high-speed systems. The Gen 2 RRG51020 MDB buffers data between the host CPU and DRAMs. Both the MRCD and MDB support speeds up to 12.8 Gbps. Optimized for high-current, low-voltage operation, the RRG53220 PMIC provides reliable electrical-over-stress protection and enhanced power efficiency.
Production availability of the RRG50120 MRCD, RRG51020 MDB, and RRG53220 PMIC is expected in the first half of 2025. To learn more about Renesas DDR5 products, click here.
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