A new UCIe IP operating at up to 40 Gbps enables more data to travel efficiently across heterogeneous and homogeneous dies—chiplets—in today’s artificial intelligence (AI)-centric data center systems. It supports organic substrates as well as high-density advanced packaging technologies, allowing designers to explore the packaging options that best fit their requirements.
The 40 G UCIe IP solution from Synopsys includes PHY, controller, and verification IP, which makes it a complete protocol stack. The PHY with a controller on top facilitates a seamless connection between two dies via on-chip interconnect protocols—including AXI, CHI C2C, CXS, PCIe, CXL, and streaming—to allow a die-to-die connection between fabrics. Verification IP comes with Synopsys 3DIC Compiler and all the required design collateral and documentation for automated routing flow, interposer studies, and signal integrity analysis.
The 40G UCIe IP is built on a silicon-proven architecture with interoperability to multiple foundry processes. Source: Synopsys
Synopsys claims its 40G UCIe IP supports 25% more bandwidth than the UCIe specification, enabling 12.9 Tbps/mm of data to travel between heterogeneous and homogeneous dies without impacting energy efficiency and silicon footprint. In other words, while complying with the latest UCIe 2.0 specification, the IP solution exceeds the standard with additional bandwidth efficiency.
“Heterogeneous integration with high-bandwidth die-to-die connectivity gives us the opportunity to deliver new memory chiplets with the efficiency needed for data-intensive AI applications,” said Jongwoo Lee, VP of system LSI IP development team at Samsung Electronics.
Key design features
The 40 G UCIe IP, while supporting both UCIe 1.1 and UCIe 2.0 standards, offers additional capabilities for designers to easily integrate die-to-die connectivity IP and simplify overall chiplet design. Start with a single clock reference that supports 100-MHz reference clocking for all UCIe PHYs, eliminating the need for additional high-frequency system PLLs.
The internal PLL generates all the high-speed peripheral clock (pclk) and lower local clock (lclk) frequencies needed during initialization and regular operation. Moreover, the lower local clock is shared with the controller to further simplify system integration. These capabilities simplify clocking architecture, optimize power, and speed up die-to-die link initialization without needing to load firmware.
Next, signal integrity monitors (SIMs) are integrated into the IP for diagnosis and analysis to ensure multi-die package reliability and quality. These test features embedded in the PHY allow high-coverage tests of the PHY at the wafer level for known good die (KGD) and after package assembly. Automotive chiplet designers can leverage the integrated SIM sensors and test and repair functions to build more reliable dies while addressing the demanding automotive requirements.
Then there are vendor-defined messages that enable the use of existing UCIe sideband channels to send low-speed, low-priority communication between dies without hampering the main data path. So, instead of interrupting the high-bandwidth path with this type of traffic, a die can use the UCIe sideband to send commands such as interrupts and telemetry to the other die.
Finally, hardware-based bring-up speeds initialization without needing to load heavy firmware on the remote chiplet. Otherwise, when a UCIe link bring-up uses heavy firmware to be loaded into the die, a separate path would be required to load the firmware. That’s wasteful and time consuming from a design standpoint.
Such capabilities and higher speeds bode well for the UCIe interconnect, a de facto standard for die-to-die connectivity. The support for advanced packaging can also make chiplets development more affordable.
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