The chiplets movement is gaining steam, and it’s apparent from how this multi-die silicon premise is dominating the program of the AI Hardware and Edge AI Summit to be held in San Jose, California from 10 to 12 September 2024. The annual summit focuses on deep tech and machine learning ecosystems to explore advancements in artificial intelligence (AI) infrastructure and edge deployments.
At the event, Alphawave Semi’s CTO Tony Chan Carusone will deliver a speech on chiplets and connectivity while showing how AI has emerged as the primary catalyst for the rise of chiplet ecosystems. “The push for custom AI hardware is rapidly evolving, and I will examine how chiplets deliver the flexibility required to create energy-efficient systems-in-package designs that balance cost, power, and performance without starting from scratch,” he said while talking about his presentation at the event.
Figure 1 Chiplets have played a vital role in creating silicon solutions for AI, and that’s extending to 6G communication, data center networking, and high-performance computing (HPC). Source: Alphawave Semi
At the summit, Alphawave Semi will showcase an advanced HBM3 sub-system designed for AI workloads as well as AresCORE, a 3-nm 24-Gbps UCI integrated with TSMC CoWoS advanced packaging. There will also be a live demonstration of die-to-die (D2D) traffic at 24 Gbps per lane.
LG’s chiplet design
Another chiplets-related announcement involves leading consumer electronics manufacturer LG Electronics, which has created a system-in-package (SiP) encompassing chiplets with processors, DDR memory interfaces, AI accelerators, and D2D interconnect. Blue Cheetah Analog Design provided its BlueLynx D2D interconnect subsystem IP for this chiplet-based design.
Figure 2 Chiplet designs demand versatile interconnect solutions that minimize die-to-die latency and support a variety of packaging requirements. Source: Blue Cheetah
BlueLynx D2D interconnect provides customizable physical (PHY) and link layer chiplet interfaces and supports both Universal Chiplet Interconnect Express (UCIe) and Bunch of Wires (BoW) standards. Moreover, the PHY IP solutions can be integrated with on-die buses using popular standards such as AMBA, CHI, AXI, and ACE.
The D2D interconnect IP is available for 16 nm, 12 nm, 7 nm, 6 nm, 5 nm, and 4 nm process nodes and works on multiple fabs. It also facilitates both standard and advanced packaging while supporting multiple bump pitches, metal stacks, and orientations.
Related Content
- Startup Tackles Chiplet Design Complexity
- How the Worlds of Chiplets and Packaging Intertwine
- Chiplets advancing one design breakthrough at a time
- Chiplets diary: Three anecdotes recount design progress
- Chiplets diary: Controller IP complies with UCIe 1.1 standard
The post Interconnect underdogs steering chiplet design bandwagon appeared first on EDN.