For most system-on-chip (SoC) designs, the most critical task is not RTL coding or even creating the chip architecture. Today, SoCs are designed primarily by assembling various silicon intellectual property (IP) blocks from multiple vendors. This makes managing silicon IP the dominant task in the design process.
Generally, less than a tenth of a new SoC design will be newly written RTL code. And often, the high-level chip architectural decisions will be clear: a variation on an existing architecture or a reflection of major data flows in the application layered on a standard bus or network-on-chip (NoC) structure.
But each piece of IP in the design—and there may be dozens of types and hundreds of instances—requires management. The chip designers must define requirements, select vendors and specific products, make any necessary customizations, set configuration parameters, and integrate the IP instances into a working, testable system. This process will consume most of the project resources until physical design.
This reality makes expertise in managing IP a significant factor in the success of an SoC design. Perhaps less obviously, access to IP—particularly the ability to get attention, detailed specifications and documentation, bug fixes, and customization support from large, influential IP vendors—becomes a critical issue. The growing complexity of the IP blocks only adds to the challenge.
Figure 1 IP management is a significant consideration in the success of an SoC design. Source: Faraday Technology
A vital partnership
This situation adds a new dimension to the familiar space of design partnerships. Many SoC design teams have used design-services companies to supplement their teams on specific skills—for example, to do physical design.
In some cases, this supplementing has broadened into a full partnership, with the design partner taking on many steps in the design process. In extreme cases, the client may only have a functional description of the SoC or a proverbial sketch on a napkin at the beginning of the engagement.
However, as IP becomes the center of attention, clients are asking design partners to shoulder IP management as well. Indeed, this can be a powerful lever for the client. Let’s look closer at what this new partnership level entails and what it implies about the ideal design partner.
Flexible engagement
Only a few SoC design relationships start on a scribbled napkin. However, in many more cases, there are some major IP blocks for which the client has only a conceptual understanding. For example, a client may know they need a low-power artificial intelligence (AI) accelerator block for an Internet of things (IoT) chip. However, they may have little information on how these complex blocks perform with different models or how they are structured internally.
Or a team may be writing code for a novel function in their SoC but have no idea how to select and configure a RISC-V CPU core to execute their new code within timing and power constraints. Yet another client may know precisely the UCIe interface requirements for their design, but not exactly how to configure any available UCIe interface IP blocks to meet those requirements.
These differences make flexible engagement vital. A design partner should be able to join the project at any level, from concept through netlist, and mesh smoothly with the client’s design team. Initially, the goal will be working with the client to refine the IP requirements—moving from concept to functional spec to detailed interface, power/performance/area, and layout requirements—so the partners can select the best IP for each instance in the design.
IP selection
With the requirements in hand, the client and design partner will select the IP to be used. At this point, the partner’s role diverges from the traditional idea of a hot-shot bunch of designers-for-hire. The depth of the partner’s relationships with IP vendors becomes crucial.
Figure 2 IP selection is now a crucial part of an SoC design project. Source: Faraday Technology
Ideally, the partner would develop and maintain their extensive IP libraries in-house. This allows the partner to match requirements against its inventory quickly. If a match is close but not perfect, the IP development team has the documentation, tools, and resources to customize the IP block for the client’s specific needs.
A partner needs many strengths beyond skilled design engineers in selecting, customizing, and licensing IP. A broad internal portfolio of silicon-verified IP, backed by the team that designed those blocks, is a huge advantage.
There will be cases when there is no close match. That brings in the IP outsource team, an engineering group exclusively charged with building and maintaining third-party IP relationships. Such a team has a vast global network of IP suppliers, ensuring it can match the client’s requirements.
A global network of time-tested IP licensing and development relationships with third-party IP vendors—and a team dedicated to maintaining that network—is essential. A client should especially investigate a prospective design partner’s relationship with ARM and with the growing ecosystem of RISC-V providers.
IP integration
The design partner will also be deeply involved in IP integration. The IP instances must be configured correctly and then connected to the chip’s underlying bus or network architecture. The correct operation of the assembled SoC design must be verified. Important subjects beyond functional design, such as test architecture, power management, and clock architecture, must be resolved—ideally, uniformly.
The first step, connectivity, begins with selecting IP blocks with the necessary interfaces. However, some blocks may require customization to meet interface requirements perfectly. In other cases, the integration team may have to create a wrapper, controller, or gateway between regions of the design. A large IP design team with this in-house expertise is a huge time saver.
Verification is an equal challenge. Often, an IP block doesn’t behave as expected—or as described—in the assembled SoC design. This is another situation where an internal IP design team is immensely valuable. Even with external IP, a design partner can usually resolve problems without bringing in a third-party vendor.
A detailed knowledge of the internals of the IP blocks is also valuable in power management and when designing for test. Blocks may be designed with specific assumptions about test strategies, the balance of built-in self-test (BIST) versus external access, sleep modes, and how to deploy power or clock gating.
These choices must be harmonized across the design to produce an SoC with a minimal test time and an effective chip-wide power-management strategy. Making those choices may require designers to get elbow-deep into the internals of the IP blocks.
Finding a partner
We have touched upon several issues that require an effective design partner to have deep expertise in IP. The ideal partner for today’s SoC designs would have its extensive internal IP portfolio and a broad network of third-party vendors.
It would have separate engineering groups supporting these two sources. It would also have a flexible engagement model that would divide tasks between client and partner teams on a block-by-block basis based on the client’s resources and expertise.
The dominance of IP in SoC design has changed the nature of the design task and what a client must expect of a design partner.
Efren Brito is technical director at Faraday Americas.
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