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What’s Arm up to in design and development of chiplets, the highly integrated large-scale silicon solutions? The IP giant is gradually unveiling its design blueprint for one of the most exciting opportunities in today’s semiconductor realm.
It’s critical that Arm ensures a place for its compute building blocks in multi-die silicon platforms, whether they are CPU chiplets or customized application-specific chiplets. So, Arm is cobbling strategic partnerships with chip design houses as well as semiconductor IP suppliers to ensure that Arm-based systems are part of the chipset revolution.
Arm is also proactively engaged in standardization efforts to define common design frameworks for chiplet designs. That matters because Arm’s Advanced Microcontroller Bus Architecture (AMBA) specifications form the bedrock of system-on-chip (SoC) connectivity designs for over two decades.
Alphawave Semi tie-up
Arm’s collaboration with chiplet IP supplier Alphawave Semi provides a few clues on the Cambridge, England-based company’s larger blueprint for multi-die silicon devices. In October 2023, Alphawave Semi joined the Arm Total Design initiative to create chiplet solutions based on Arm Neoverse Compute Subsystems (CSS).
Alphawave Semi would integrate Arm Neoverse CSS compute with its Universal Chiplet Express (UCIe)-enabled custom silicon and pre-built connectivity chiplets. Therefore, its UCIe IP would support Arm fabric interfaces such as Advanced eXtensible Interface (AXI) and Coherent Hub Interface (CHI), enabling easy integration of connectivity for interfaces such as CXL, HBMx, DDRx, and Ethernet onto Arm-based custom SoCs and chiplets.
In short, Alphawave Semi would combine its high-speed connectivity IP and chiplet platforms with Arm Neoverse CSS reference IP solution. Moreover, its specialized team would harden and optimize the Neoverse cores for power, performance, and area (PPA) in major process nodes scaling down to 3-nm and 2-nm chiplet manufacturing.
Fast forward to June 2024, when Alphawave Semi announced the development of an advanced compute chiplet built on the Arm Neoverse CSS platform for artificial intelligence (AI) and machine learning (ML), high-performance compute (HPC), data center, and 5G/6G networking infrastructure applications. The tie-up added significant differentiators to Alphawave Semi’s design platform, including I/O extension chiplets, memory chiplets, and compute chiplets.
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Figure 1 The compute chiplet features an Arm Neoverse N3 CPU core cluster and the Arm Coherent Mesh Network (CMN). Source: Arm
Arm has also partnered with Japanese design house Socionext to develop a 32-core CPU chiplet on TSMCʼs 2-nm process node. The CPU chiplet, built around the Arm Neoverse CSS platform, is designed for single or multiple instantiations within a single package. It also includes I/O and application-specific custom chiplets to optimize performance for a variety of applications.
Arm’s chiplet blueprint
A recent blog from Richard Grisenthwaite, executive VP, chief architect and Fellow at Arm, provides a few clues on the company’s chiplet design blueprint. For a start, it has launched the Arm Chiplet System Architecture (CSA) initiative to enable greater reuse of components like PHY IP and soft IP among multiple suppliers.
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Figure 2 Leveraging Neoverse CSS compute, CSA aims to set the foundation for a robust chiplet environment. Source: Arm
The initiative, comprising more than 20 partners, is analyzing and defining optimal partitioning choices for chiplet-based systems. It’s also exploring new ways to better standardize system design choices for different chiplet types.
Next, Arm is updating AMBA specifications for on-chip and off-chip interfaces for chiplet designs. Arm’s AMBA specifications, such as AXI and CHI, have been used in billions of semiconductor devices.
Arm is also an active participant in efforts to create industry standards like UCIe, which define the physical layer (PHY) for transporting data between chiplets within a package. Besides bringing the SoC interconnect protocols like AMBA to chiplet designs, Arm is engaged in efforts to adopt industry standards like PCIe and CXL to aggregate well-defined peripherals from across a motherboard into a package.
Finally, as part of efforts to create alignment on many non-differentiating choices in chiplet partitioning, Arm is exploring to disaggregate the SoC into chiplets for Arm-based systems using AMBA protocols. Such initiatives are meant to expedite the design journey toward chiplet-based systems.
Chiplet partitioning framework
Arm’s investments in AMBA and CSA domains demonstrate how it’s trying to decompose an Arm-based system across multiple chiplets. That’s crucial because reusability can create interesting new possibilities in the thriving chiplet marketplace. Collaboration with connectivity IP specialists like Alphawave Semi seems part of this effort to streamline chiplet partitioning.
Still, standards enabling a common framework will play a vital role in creating viable chiplet solutions, and that’s why Arm is proactively engaged on UCIe and other standardization fronts. Its own initiative CSA is aiming to create a consensus around the most valuable partitioning schemes to reduce fragmentation.
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