As system-on-chip (SoC) designs become more complex and powerful, catching potential errors and issues in specifications at the front-end of the design cycle is now far more critical. An EDA outfit based in Gentbrugge, Belgium, claims to have employed a shift left of simulation and synthesis tasks to catch specification errors early in the chip design cycle and fix inefficiencies in hardware description language (HDL)-based design flow.
The traditional HDL-based design flow is no longer viable, says Dieter Therssen, CEO of Sigasi, a privately held and self-funded firm founded in 2008. That’s because the traditional HDL workflow cannot accommodate the massive amounts of design specifications encompassing high-level synthesis results, complex SoC intellectual property (IP), and special features like generative artificial intelligence (genAI) creations.
Such levels of abstraction call for a plug-and-play approach for large HDL files containing functionality created with domain-specific knowledge to integrate hundreds of billions of transistors on a chip. In other words, HDL creation, integration, and validation must be redefined for the chip design cycle to fix the inefficient HDL-based design flow.
Therssen claims that Sigasi’s new HDL portfolio provides hardware designers and verification engineers the workflow makeover they need, enabling them to work in a powerful environment to create, integrate, and validate their designs while leveraging shift-left principles. Sigasi Visual HDL portfolio, an integrated development environment (IDE), employs the shift-left methodology to give hardware designers and verification engineers better insight during the design process.
It enables them to easily manage HDL specifications by validating code early in the design flow, well before simulation and synthesis flows. So, it’s a shift left of simulation and synthesis tasks, which flags problems while users enter the HDL code. While doing so, it enforces coding styles as recommended by safety standards such as DO-254 or ISO 26262 and catches Universal Verification Methodology (UVM) abuses.
Sigasi Visual HDL or SVH is fully integrated with Microsoft’s Visual Studio Code (VS Code), the most popular IDE according to Stack Overflow’s 2019 survey. That allows hardware designers and verification engineers to use git, GitHub Source Control Management, and a selection of utilities to facilitate mundane tasks like extracting TODO comments or bookmarking important sections in HDL code.
Sigasi Visual HDL will be available at the end of June 2024.
Sigasi Visual HDL, built as a tiered portfolio, offers three commercial editions and one community edition to meet specific SoC design and verification challenges.
- Designer Edition
It meets the specific requirements of individual engineers who need introspection of their HDL projects. The Designer Edition includes all the essential guidelines and tools to create quality code, from hovers and autocompletes to quick fixes, formatting, and rename refactoring.
- Professional Edition
It builds on the Designer Edition to incorporate more complex features focused on verifying HDL specifications. That includes graphic features like block diagrams and state machine views as well as UVM support.
- Enterprise Edition
It offers features needed by large engineering teams, including command-line interface capabilities to safeguard the code repository and ensure a better handoff to verification groups. The Enterprise Edition also includes documentation generation as part of a better HDL handoff.
- Community Edition
It lets users explore its features for non-commercial uses and is commonly used by students and teachers who want to better learn the fundamentals of HDL design. So, students no longer need to request a limited-time educational license; they can download the VS Code extension and upgrade their HDL education.
Sigasi Visual HDL—to be made available at the end of June 2024—will be displayed at Booth #2416 on second floor during Design Automation Conference (DAC) at Moscone West in San Francisco on 24-26 June 2024.
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