In order to test multiple ICs simultaneously with different test voltages and currents, semiconductor automatic test equipment (ATE) uses multiple source measurement units (SMUs). Each SMU requires its own independent floating voltage tracking power supply to ensure clean measurements.

Figure 1 shows the basic structure of the SMU power supply. The voltage tracking power supplies need to supply the power amplifiers with a wide voltage range (±15 V to ±50 V) and a constant power capability.

Figure 1 A simplified power-supply block diagram in an ATE. Source: Texas Instruments

Figure 2 illustrates the maximum steady-state voltage and current that the SMU requires in red and the pulsed maximums in blue.

Figure 2 An example voltage-current profile for a voltage tracking power supply. Source: Texas Instruments

The ICs under test require a low-noise power supply with minimal power loss. In order to manage the power dissipation in a linear power device and deliver constant power under the conditions shown in Figure 2, it is required that the power supply be able to generate a pulsating output with high instantaneous power.

In addition to power dissipation considerations, it is essential that the power supply has a sufficient efficiency and thermal management to accommodate as many test channels as possible.

Four topologies are studied and compared to see which one best meets the voltage tracking power supply requirements. Table 1 lists the electrical and mechanical specifications for the power supply. The four topologies under consideration are: hard-switching full bridge (HSFB), full-bridge inductor-inductor-capacitor (FB-LLC) resonant converter, dual active half bridge (DAHB), and a two-stage approach composed of a four-switch buck-boost (4sw-BB) plus half-bridge LLC resonant converter (HB-LLC).

Table 1 Electrical and mechanical SMU requirements. Source: Texas Instruments

Topology comparison

Figure 3 shows the schematic for each of the four power supplies.

Figure 3 The four topologies evaluated to see which one best meets the voltage tracking power supply requirements listed in Table 1. Source: Texas Instruments

Each topology was evaluated on two essential requirements: small size and minimizing the thermal footprint. Efficiency is only important in as far as heat management is concerned.

Table 2 summarizes the potential benefits and challenges of each topology. In addition to size, the maximum height constraint necessitates a printed circuit board (PCB)-based transformer design.

Table 2 The benefits and challenges of the four different SMU power supply topologies. Source: Texas Instruments

In order to understand the size implications for the HSFB, it is necessary to start out by examining the structure of the transformer. Equation 1 calculates the turns ratio for the HSFB as:

Using the requirements listed in Table 1 gives a result of . Because a practical design will require a PCB with no more than 18 layers, the maximum required primary turns on a center-tapped design is 2:8:8. With this information, you can use Equation 2 to estimate the center leg core diameter:

Hard switching losses in the FETs will keep the frequency no higher than 500 kHz, resulting in a 12 mm diameter of the center leg. The resulting core will be at least twice this size. The end result is that the HSFB solution is just too large for any serious practical consideration.

The single-stage FB-LLC enables a higher switching frequency by solving the hard-switching concerns found in the HSFB. However, the broad input and output voltage range will require a small magnetizing inductance. The best design identified used a turns ratio of 4:5, L_m = 2 µH, L_r = 1 µH, and f_r = 800 kHz. This design addresses the issues with the HSFB by incorporating more primary turns, achieving a high operating frequency for minimal size, and requiring only 14 layers. However, the design suffers from several operating points that result in ZVS loss and an inability to generate the necessary output voltage under pulsed load conditions.

Figure 4 shows the equation and plots of the maximum gain of the system. Supporting the requirements outlined in Table 1 requires a gain of at least 3. Figure 4 shows that this is only possible by drastically decreasing one or more of L_r, L_m, or f_r. Decreasing L_r will result in a loss of ZVS from the rapid change in the inductor current. Reducing f_r will drive up the size of the transformer and the required primary turns. Decreasing L_m will significantly increase losses from additional circulating current. Given these factors, the single-stage FB-LLC is also not an option.

Figure 4 Maximum fundamental harmonic approximation (FHA) gain plots. Source: Texas Instruments

DAHB

The DAHB [1] is an interesting option that also attempts to solve the hard-switching concerns. One area of concern is the requirement to have active control of the secondary FETs. This kind of control will require additional circuitry to translate the control across the isolation boundary. Equation 3 predicts the resulting power delivery capability of the DAHB:

Table 3 lists the results for the full requirements outlined in Table 1. Notice that there are several problematic conditions, most notably one condition where the required peak current is 80 A. The FETs used in the design cannot accommodate this current.

Table 3 DAHB operating points with several problematic conditions that cannot be designed. Source: Texas Instruments

The two-stage approach pushes the voltage regulation problem to the 4sw-BB and operates the HB-LLC at a fixed frequency at resonance, which allows the HB-LLC to run at high frequency and more easily achieve ZVS under all conditions. The obvious downside of this approach is that it uses two power stages instead of one. However, the reduced currents in the HB-LLC and its ability to run at higher frequencies enable you to minimize the size of the transformer.

Table 4 summarizes the comparison between the four topologies, highlighting the reasons for selecting the two-stage approach. References [2] and [3] describe some essential control parameters used for the buck-boost and LLC.

 Table 4 Comparison between the four different topologies, highlighting the reasons for selecting the two-stage approach. Source: Texas Instruments

Test results

Based on the comparison results, I built a high-power-density (14 mm by 45 mm) 4sw-BB plus HB-LLC prototype. Figure 5 shows an image of the hardware prototype of the final design that fits in the space outlined by Table 1.

Figure 5 The top-side layout of the high-power density 4sw-BB + HB-LLC test board. Source: Texas Instruments

Figure 6 shows both efficiency and thermal performance of the LLC converter.

Figure 6 The LLC efficiency curve and a thermal scan of the LLC converter. Source: Texas Instruments

Two-stage approach

After considering four topologies to meet ATE SMU requirements, the two-stage approach with the four-switch buck boost and fixed-frequency LLC was the smallest overall solution capable of meeting the system requirements.

Brent McDonald works as a system engineer for the Texas Instruments Power Supply Design Services team, where he creates reference designs for a variety of high-power applications. Brent received a bachelor’s degree in electrical engineering from the University of Wisconsin-Milwaukee, and a master’s degree, also in electrical engineering, from the University of Colorado Boulder.

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References

1. Laturkar, N. Deshmukh and S. Anand. “Dual Active Half Bridge Converter with Integrated Active Power Decoupling for On-Board EV Charger.” 2022 IEEE International Conference on Power Electronics, Smart Grid, and Renewable Energy (PESGRE), Trivandrum, India, 2022, pp. 1-6, doi: 10.1109/PESGRE52268.2022.9715900.
2. McDonald and F. Wang.” LLC performance enhancements with frequency and phase shift modulation control.” 2014 IEEE Applied Power Electronics Conference and Exposition – APEC 2014, Fort Worth, TX, USA, 2014, pp. 2036-2040, doi: 10.1109/APEC.2014.6803586.
3. Sun, B. “Multimode control for a four-switch buck-boost converter.” Texas Instruments Analog Design Journal, literature No. SLYT765, 1Q 2019.

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