Semiconductor compute has grown drastically over the past 18 to 24 months amid the vast artificial intelligence (AI) infrastructure buildup. Nvidia and hyperscalers have made many announcements about migrating to GPUs with 200 Gbps per lane speeds. However, with computation moving to higher data rates, optical connectivity must also migrate to higher data rates.
But here comes the rub. While the rapid growth of AI workloads drives demand for increased bandwidth and interconnect density in AI clusters, optical interconnect power is a major factor limiting cluster scalability. Broadcom claims its new Sian3 and Sian2M PHY chips supporting 200 G/lane speeds offer greater levels of power efficiency and cost optimization for next-generation AI infrastructure.
Figure 1 Sian3 and Sian2M DSP PHYs enable module developers to rapidly address the growing demand for 200G optics in AI. Source: Broadcom
Optical connections can be short-reach or long-reach because sometimes AI clusters are in two different buildings. Natarajan Ramachandran, director of product line management for Broadcom’s Physical Layer Products Division, told EDN that Sian2M and Sian3 devices address these two scenarios, respectively.
Sian2M PHY chips
Ramachandran said that for shorter distances of less than 100 m, traditional optics, commonly termed multi-mode optics (MMF), is used. Here, vertical-cavity surface-emitting laser (VCSEL) technology has scaled very well so far. “However, in transition from 800 Gbps to 1.6 Tbps, VCSELs increasingly face physics limitations, making short-link bandwidths hugely constrained.”
Sian2M provides an optimized solution for 800G and 1.6T short-reach MMF links within AI clusters. It’s the first 200 G/lane DSP with integrated VCSEL drivers that enables low-power short-reach MMF links in AI clusters. “While industry watchers mostly believed that short link optics has reached a dead end, we are extending its life by at least one more generation,” Ramachandran said.
For longer distances of 2 Km to 3 Km operating across single-mode fiber (SMF) links, problems lie in power consumption. At 800 Gbps, power consumption was 15-16 W; but when you go to 1.6 Tbps, you don’t want to double the power usage. Enter Sian3 PHY chip.
Figure 2 Sian3 and Sian2M DSPs optimize power across single-mode fiber (SMF) and short-reach multi-mode fiber (MMF) links in 800G and 1.6T optical transceiver applications. Source: Broadcom
Sian3 PHY chips
At GTC 2025, held in San Jose, California, from 17 to 21 March, Nvidia’s chief Jensen Huang stressed the need for picojoule per bit to come down. That’s where Sian3 comes in, said Ramachandran. “We achieved 28 W with Sian2 while competition is roughly at 32 W,” he added. “With Sian3, a follow-on to Sian2, the transition from 5 nm to 3nm node results in 5-W savings, bringing power consumption down to 23 W.”
“So, we are getting close to what we’ve been consuming at 800 Gbps while moving to 1.6 Tbps speeds,” Ramachandran said. “And picojoule per bit is also showing a nice downward trend.” He also stated Broadcom’s aim to lower power consumption numbers, eventually reaching less than 20 W.
But is the cost also going down? Besides picojoule per bit, what about dollar per bit? Ramachandran said that with the transition from 5-nm to 3-nm process node, the die size also shrinks a lot, which significantly impacts the cost.
Broadcom is sampling Sian3 and Sian2M chips to early access customers and partners; Sian3 production is ramping up in the third quarter of 2025. Broadcom will demonstrate Sian chips and 200G VCSEL operating inside 1.6T optical modules at OFC in San Francisco, California, to be held on 1-3 April 2025.
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