Due to their versatility, ease of design, and low cost, flyback converters have become one of the most widely used topologies in power electronics. Its structure derives from one of the three basic topologies—specifically, buck-boost topology. However, unlike buck-boost converters, flyback topologies allow the voltage output to be electrically isolated from the input power supply. This feature is vital for industrial and consumer applications.
Among the different control methods used to stabilize power converters, the most widely used control method is peak current mode, which continuously senses the primary current to provide important protection for the power supply.
Additionally, to obtain a higher design performance, it’s common to regulate the converter with the output that has the highest load using a technique called cross-regulation.
This article aims to show engineers how to correctly design the control loop that stabilizes the flyback converter in order to provide optimal functionality. This process includes minimizing the stationary error, increasing/decreasing the bandwidth as required, and increasing the phase/gain margin as much as possible.
Closed-loop flyback converter block diagram
Before making the necessary calculations for the controller to stabilize the peak current control mode flyback, it’s important to understand the components of the entire closed-loop system: the converter averaged model and the control loop (Figure 1).
Figure 1 Here is how the components look in the entire closed-loop system. Source: Monolithic Power Systems
The design engineer’s main interest is to study the behavior of the converter under load changes. Considering a fixed input voltage (VIN), the open-loop transfer function can be modeled under small perturbations produced in the duty cycle to study the power supply’s dynamic response.
The summarized open-loop system can be modeled with Equation 1: 
(1)
Where G is the current-sense gain transformed to voltage and GC(s) and GCI(s) are the transfer functions of the flyback converter in terms of output voltage and magnetizing current response (respectively) under small perturbations in the duty cycle. GαTS is the modeling of the ramp compensation to avoid the double-pole oscillation at half of the switching frequency.
Flyback converter control design
There are many decisions and tradeoffs involved in designing the flyback converter’s control loop. The following sections of the article will explain the design process step by step. Figure 2 shows the design flow.
Figure 2 The design flow highlights control loop creation step by step. Source: Monolithic Power Systems
Control loop design process and calculations
Step 1: Design inputs
Once the converter’s main parameters have been designed according to the relevant specifications, it’s time to define the parameters as inputs for the control loop design. These parameters include the input and output voltages (VIN and VOUT, respectively), operation mode, switching frequency (fSW), duty cycle, magnetizing inductance (LM), turns ratio (NP:NS), shunt resistor (RSHUNT), and output capacitance (COUT). Table 1 shows a summary of the design inputs for the circuit discussed in this article.
Table 1 Here is a summary of design inputs required for creating control loop. Source: Monolithic Power Systems
To design a flyback converter compensator, it’s necessary to first obtain all main components that make the converter. Here, HF500-40 flyback regulator is used to demonstrate design of a compensator using optocoupler feedback. This device is a fixed-frequency, current-mode regulator with built-in slope compensation. Because the converter works in continuous conduction mode (CCM) at low line input, a double-pole oscillation at half of the switching frequency is produced; built-in slope compensation dampens this oscillation, making its effect almost null.
Step 2: Calculate parameters of the open-loop transfer function
It’s vital to calculate the parameters of the open-loop transfer function and calculate the values for all of the compensator’s parameters that can optimize the converter at the dynamic behavior level.
The open-loop transfer function of the peak current control flyback converter (also including the compensation ramp factor) can be estimated with Equation 2:
(2)
Where D’ is defined by the percentage of time that the secondary diode (or synchronous FET) is active during a switching cycle.
The basic canonical model can be defined with Equation 3: 
(3)
Note that the equivalent series resistance (ESR) effect on the output capacitors has been included in the transfer function, as it’s the most significant parasitic effect.
By using Equation 2 and Equation 3, it’s possible to calculate the vital parameters.
The resonant frequency (fO) can be calculated with Equation 4:
(4)
After inputting the relevant values, fO can be calculated with Equation 5: 
(5)
The right-half-plane zero (fRHP) can be estimated with Equation 6: 
(6)
The q-factor (Q) can be calculated with Equation 7: 
(7)
After inputting the relevant values, Q can be estimated with Equation 8: 
(8)
The DC gain (K) can be calculated with Equation 9: 
(9)
After inputting the relevant values, K can be estimated with Equation 10: 
(10)
The high-frequency zero (fHF) can be calculated with Equation 11:
(11)
It’s important to note that with current mode control, it’s common to obtain values well below 0.5 for Q. With this in mind, the result of the second-degree polynomial in the denominator of the transfer function ends up giving two real and negative poles. This is different from voltage-control mode or when there is a very large compensation ramp, which results in two complex conjugate poles.
The two real and negative poles can be estimated with Equation 12: 
(12)
The new open-loop transfer function can be calculated with Equation 13: 
(13)
The cutoff frequency (fC) can be estimated with Equation 14: 
(14)
The following sections will explain how the frequency compensator design achieves power supply stability and excellent performance.
Step 3: Frequency compensator design
Once the open-loop transfer function is modeled, it’s necessary to design the frequency compensator such that it achieves the best performance possible. Because the frequency response of the above transfer function has two separate poles—one at a low frequency and one at a high frequency—a simple Type II compensator can be designed. This compensator does not need an additional zero, which is not the case in voltage-control mode because there is a double pole that produces a resonance.
To minimize the steady-state error, it’s necessary to design an inverted-zero (or a pole at the origin) because it produces higher gains at low frequencies. To ensure that the system’s stability is not impacted, the frequency must be at least 10 times lower than the first pole, calculated with Equation 15:
(15)
Due to the ESR parasitic effect at high frequencies, it’s necessary to design a high-frequency pole to compensate for and remove this effect. The pole can be estimated with Equation 16:
(16)
On the other hand, it’s common to modify the cutoff frequency to achieve a higher or lower bandwidth and produce faster or slower dynamic responses, respectively. Once the cutoff frequency is selected (in this case, fC is increased up to 6.5 kHz, or 10% of fSW), the compensator’s middle-frequency gain can be calculated with Equation 17: 
(17)
Once the compensator has been designed within the frequency range, calculate the values of the passive components.
Step 4: Design the compensator’s passive components
The most common Type II compensator used for stabilization in current control mode flyback converters with cross-regulation is made up of an optocoupler feedback (Figure 3).
Figure 3 Type-II compensator is made up with optocoupler feedback. Source: Monolithic Power Systems
The compensator transfer function based on optocoupler feedback can be estimated with Equation 18: 
(18)
The middle-frequency gain is formed in two stages: the optocoupler gain and the adjustable voltage reference compensator gain, calculated with Equation 19:
(19)
It’s important to calculate the maximum resistance to correctly bias the optocoupler. This resistance can be estimated with Equation 20:
(20)
The parameters necessary to calculate RD can be found in the optocoupler and the adjustable voltage reference datasheets. Table 2 shows the typical values for these parameters from the optocoupler.
Table 2 Here are the main optocoupler parameters. Source: Monolithic Power Systems
Table 3 shows the typical values for these parameters from the adjustable voltage reference.
Table 3 The above data shows adjustable voltage reference parameters. Source: Monolithic Power Systems
Once the above parameters have been obtained, RD can be calculated with Equation 21: 
(21)
Once the value of R3 is obtained (in this case, R3 is internal to the HF500-40 controller, with a minimum value of 12 kΩ), as well as the values for R1, R2, and RD (where RD = 2 kΩ), RF can be estimated with Equation 22:
(22)
Where GCOMP is the compensator’s middle frequency gain, calculated with Equation (17). GCOMP is used to adjust the power supply’s bandwidth.
Because the inverted zero and high-frequency pole were already calculated, CF and CFB can be calculated with Equation 23 and Equation 24, respectively. 
(23) 
(24)
Once the open-loop system and compensator have been designed, the loop gain transfer function can be estimated with Equation 25: 
(25)
Equation 25 is based on Equation 13 and Equation 18.
It’s important to calculate the phase and gain margins to ensure the stability of power supply.
The phase margin can be calculated with Equation 26: 
(26)
After inputting the relevant values, the phase margin can be calculated with Equation 27: 
(27)
If the phase margin exceeds 50°, it’s an important parameter necessary to comply with certain standards.
At the same time, the gain margin can be approximated with Equation 28: 
(28)
Equation 29 is derived from Equation 25 at the specified frequency:
(29)
In this scenario, the gain margin is below -10dB, which is another important parameter to consider, particularly regarding compliance with regulation specifications. If the result is close to 0dB, some iteration is necessary to decrease the value; otherwise, the performance is suboptimal. This iteration must start by decreasing the value of the cutoff frequency.
This complete transfer function provides stability to the power supply and the best performance made possible by:
- Minimizing steady-state error
- Minimizing ESR parasitic effect
- Increasing bandwidth of power supply up to 6.5 kHz
Final design
After calculating all the passive component values for the feedback loop compensator and determining the converter’s main parameters, the entire flyback can be designed using the flyback regulator. Figure 4 shows the circuit’s final design using all calculated parameters.
Figure 4 Here is how the final design circuit schematic looks like. Source: Monolithic Power Systems
Figure 5 shows the bode plot of the complete loop gain frequency response.
Figure 5 Bode plot is shown for the complete loop gain frequency response. Source: Monolithic Power Systems
Obtaining the flyback averaged model via small-signal analysis is a complex process to most accurate approximation of the converter’s transfer functions. In addition, the cross-regulation technique involves secondary-side regulation through optocoupler feedback and an adjustable voltage reference, which complicates calculations.
However, by following the four steps explained in this article, a good approximation can be obtained to improve the power supply’s performance, as the output with the heaviest load is directly regulated. This means that the output can react quickly to load changes.
Joan Mampel is application engineer at Monolithic Power Systems (MPS).
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