Texas Instruments’ APEC-related releases are power management chips centered around supporting the AI-driven power demands in data centers. The releases include the first 48-V integrated hot-swap eFuse with power-path protection (TPS1685) and an integrated GaN power stage (gate driver + FET) in the industry-standard TOLL package. 

In a conversation with Priya Thanigai, VP and Business Unit Manager of power switches at Texas Instruments, EDN obtained some insights on meeting the needs of next-generation racks demanding the 48-V architecture.

Spotlight on data centers

Hot topics at APEC typically encompassed the use of wide bandgap semiconductors like silicon carbide (SiC) and gallium nitride (GaN) to yield higher efficiency subsystems in the steady electrification of technologies. Electrified end applications have spanned from e-mobility to industrial processes that are enabled by battery and smart grid advancements. 

Discussions this year have shifted more toward the power demands that generative AI has created for data centers. While much of the actual power consumption of these data centers remains secretive, it’s apparent that LLMs like ChatGPT and DeepSeek have created a substantial increase; the U.S. data center electricity usage tripled from 2014 to 2023 according to the U.S. department of energy (DoE). The number is anticipated to double or triple by 2028.

The international energy agency (IEA) also reported that data centers consumed ~1.4-1.7% of global electricity in 2022; this is also expected to double by 2026. According to the World Economic Forum, “the computational power needed for sustaining AI’s growth is doubling roughly every 100 days.”

Going nuclear

Hyperscalers are also making more apparent their plans to sustain the energy demands. In September 2024, plans to recommission the Three Mile Island nuclear plant were made public with a 20-year contract to help power Microsoft data centers. Other technology companies follow a similar nuclear path, augmenting power capabilities with small modular reactors (SMRs).

And as the semiconductor industry is feverishly fabricating chips that can efficiently run these compute-intensive training tasks through software-hardware codesign, the power demands continually soar. Further into the future, these nuclear reactors could be used with solid-state transformers to support data center processing.

The 48-V bus and beyond

The data center server room consists of a sea of IT racks supported by a sidecar that holds hot-swappable power supply units (PSUs) that facilitate replacing or upgrading a PSU without shutting down the server (Figure 1). These PSUs support much higher power densities moving from 6 kW with the 48-V bus to 100 MW with the 400-V bus.

Figure 1: Sidecar, IT rack, and supporting subsystems shown at the TI booth during APEC 2025. 

“While data centers have been ahead of the curve, cars are only now moving to 48 V,” said Thanigai. “But data centers have probably already been there for about a decade.” It’s just been very slow because earlier systems really didn’t need the compute power until LLMs exploded. Until then, it was only the high-end GPUs that needed that extra power at 48 V.

She mentioned how TI had been keeping a watchful eye on the relatively slow move from 12-V products for data centers 48-V and how recent pressures have brought on that inflection point. “Now we’re seeing more native 48-V systems ship and we’re talking about 400-V already,” Thanigai said. “So the transition from 12 V to 48 V may have taken a decade to hit the inflection point but 48 V to 400 V will probably be shorter and sharper because of how much energy is needed by data centers.”

Moving from discretes to integrated eFuses

Power path protection is tied directly to PSU reliability and is therefore a critical aspect of ensuring zero downtime deployments. The 48-V eFuse is a successor to the popular 12-V eFuse category; the shift to 48 V allows users to scale power to beyond 6 kW. 

“If you’re looking at the power design transition, generally power architectures will begin with discretes at the start of any design because they want to get a good feel of how to build something,” explained Thanigai. The building blocks of power path protection generally include the power FET, a gate or voltage drive to drive it, and components like a soft-start capacitor to control the inrush, comparators, and current-sense elements.

Thanigai described the moves toward more integration where the hot swap controller integrates the amplifiers, some of the protection features, and some of the smarts. However, there still remains an external FET and sensing element. 

“The last leg of the integration is eFuse where the FET, the controller, and all the smarts are in a single chip,” she said. “That’s a classic power design evolution, where you go from discrete to semi-integrated to fully integrated.” The TPS1685 eFuse includes protection features like rapid response to fault events with an integrated black box for fault logging. Then there is a user-configurable overcurrent blanking timer that avoids false tripping at peak inrush.

Advanced stacking for loads > 6 kW

Mismatches in the on-state resistance (R_dson) due to PCB trace resistance and comparator thresholds can create false tripping (Figure 2). The conventional discrete designs require power architects to hand calculate the margins to make sure the FETs are matched such that no single FET is taking on more thermal stress than the others.  

Figure 2: Discrete implementations require individual calculations per sense element and FET to take into account mismatches at each node; instead R_dson is actively adjusted via V_gs regulation and equal steady-state current across all devices is achieved through path resistance equalization. Source: Texas Instruments 

The IP in the TPS1685 eFuse actively measures and monitors the thermal stress at various areas of the FET within each of the eFuses and balances current between each automatically through a single-wire protocol. The integration designates one eFuse as the primary controller to monitor total system current by using the interconnected IMON pins, enabling active R_DS(ON) shifting to ensure devices are current-sharing.

“You can basically stack unlimited eFuses,” said Thanigai, “We’ve shown up to 12 operational eFuses on a customer board and each of them can do 1 kW (~ 50 V @ 20 A), so we easily reach the 5-10 kW that you see with systems nowadays. But we can scale higher than that since there’s no upper limit.”

Figure 3: Image of 6 eFuses stacked in parallel on the top and bottom of a PCB to support a maximum load current of 120 A. 

Moving toward 400 V

When asked about the move toward supporting 400-V bus architectures, Thanigai responded, “There’s two aspects in these eFuses.” There’s the pure analog power domain, which is the FET architectures, and then there’s the digital domain which embodies smarts around the FET, she added.

All of the digital IP TI has developed scales from 12 V to 48 V to 400 V, and that while this particular device includes 48-V power FETs, TI is preparing to scale this up to 400 V.

Aalyia Shaukat, associate editor at EDN, has worked in the design publishing industry for six years. She holds a Bachelor’s degree in electrical engineering from Rochester Institute of Technology, and has published works in major EE journals as well as trade publications.

Related Content

• Telecom/Datacom 48V: Have no fear; 400V is here
• Power Tips #139: How to simplify AC/DC flyback design with a self-biased converter
• CES 2025: Moving toward software-defined vehicles
• Data center next generation power supply solutions for improved efficiency

The post Data center power meets rising energy demands amid AI boom appeared first on EDN.