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It’s remarkable how many switching regulator chips use the same basic two-resistor network for output voltage programming. Figure 1 illustrates this feature in a typical (buck type) regulator. See R1 and R2 where:
Vout = Vsense(R1/R2 + 1) = 0.8v(11.5 + 1) = 10v
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Figure 1 Typical regulator output voltage programming with a basic two-resistor network.
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Quantitatively, the Vsense feedback node voltage varies from type to type and recommended values for R1 can vary too, but the topology doesn’t. Most conform faithfully to Figure 1. This defacto uniformity is useful if your application needs digital control of Vout via PWM.
Figure 2 shows the simplistic three-component solution it makes possible where:
Vout = Vsense(R1/(R2 + R3/DF) + 1) = 0.8v to 10v as DF = 0 to 1
All that’s required to add PWM control to Figure 1 is to split R2 into two equal halves, connect filter cap Cf to the middle of the pair, and add PWM switch Q1 in series with its ground end.
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Figure 2 Simple circuit for regulator programming with PWM where Vout ranges from 0.8 V to 10 V as the duty factor (DF) goes from 0 to 1.
The Cf capacitance required for 1-lsb PWM ripple attenuation is 2(N-2)Tpwm/R2, where N is number of PWM bits and Tpwm is the PWM period. Since Cf will never see more than perhaps a volt, its voltage rating isn’t much of an issue.
A cool feature of this simple topology is that, unlike many other schemes for digital power supply control, only the regulator’s internal voltage reference matters to regulation accuracy. Precision is therefore independent of external voltage sources, e.g. logic rails. This is a good thing because, for example, the tempco of the TPS54332’s reference is only 15 ppm/oC.
Figure 3 graphs Vout versus the PWM DF for the Figure 2 circuit where the X-axis is DF, the Y-axis is Vout and,
Vout = Vsense(R1/(R2 + R3/DF) + 1)
Vout(min) = Vsense
Vout(max) = Vsense(R1/(R2 + R3) + 1)
R1/(R2 + R3) = Vout(max)/Vsense – 1
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Figure 3 Graph showing Vout versus the Figure 2 PWM DF.
Figure 4 plots the inverse function with DF vs Vout where,
DF = R3/(R1/(Vout/Vsense – 1) – R2)
The nonlinearity of DF versus Vout does incur the cost of a bit of software complexity (two subtractions and three divisions) to do the conversion. But since it buys substantial circuitry simplification, it seems a reasonable (maybe zero) cost. Or, if the necessary memory is available, a lookup table is another (simple!) possibility.
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Figure 4 DF versus Vout; the non-linearity necessitates a bit of software complexity to perform the conversion.
Stephen Woodward’s relationship with EDN’s DI column goes back quite a long way. Over 100 submissions have been accepted since his first contribution back in 1974.
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