For decades, compute architectures have relied on dynamic random-access memory (DRAM) as their main memory, providing temporary storage from which processing units retrieve data and program code. The high-speed operation, large integration density, cost-effectiveness, and excellent reliability have contributed to the widespread adoption of DRAM technology in many electronic devices.
DRAM bit cell—the element that stores one bit of information—has a very basic structure. It consists of one capacitor (1C) and one transistor (1T) integrated close to the capacitor. While the capacitor’s role is to store a charge, the transistor is used to access the capacitor, either to read how much charge is stored or to store a new charge.
The 1T-1C bit cells are arranged in arrays containing word and bit lines, and the word line is connected to the transistors’ gate, which controls access to the capacitor. The memory state can be read by sensing the stored charge on the capacitor via the bit line.
Over the years, the memory community introduced subsequent generations of DRAM technology, enabled by continuous bit-cell density scaling. Current DRAM chips belong to the ’10-nm class’ (denoted as D1x, D1y, D1z, D1a…), where the half pitches of the active area in the memory cell array range from 19 nm down to 10 nm. However, the AI-driven demand for better performing and larger capacity DRAM is propelling R&D into beyond 10-nm generations.
This requires innovations in capacitors, access transistors, and bit cell architectures. Examples of such innovations are high-aspect ratio pillar capacitors, the move from saddle-shaped (FinFET-based) access transistors to vertical-gate architectures, and the transition from 6F2 to 4F2 cell designs—F being the minimum feature size for a given technology node.
A closer look inside a planar 1T-1C DRAM chip: The peripheral circuit
To enable full functionality of the DRAM chip, several other transistors are needed besides the access transistors. These additional transistors play a role in, for example, the address decoder, sense amplifier, or output buffer function. They are called DRAM peripheral transistors and are traditionally fabricated next to the DRAM memory array area.
Figure 1 The 1T-1C-based DRAM memory array and DRAM peripheral area are shown inside a DRAM chip. Source: imec
DRAM peripheral transistors can be grouped into three main categories. The first category is regular logic transistors: digital switches that are repeatedly turned on and off. The second category is sense amplifiers—analog types of transistors that sense the difference in charge between two-bit cells. A small positive change is amplified into a high voltage (representing a logic 1) and a small negative change into zero voltage (representing a logical 0).
These logical values are then stored in a structure of latches called the row buffer. The sense amplifiers typically reside close to the memory array, consuming a significant area of the DRAM chip. The third category is row decoders: transistors that pass a relatively high bias (typically around 3 V) to the memory element to support the write operation.
To keep pace with the node-to-node improvement of the memory array, the DRAM periphery evolves accordingly in terms of area reduction and performance enhancement. In the longer term, more disruptive solutions may be envisioned that break the traditional ‘2D’ DRAM chip architecture. One option is to fabricate the DRAM periphery on a separate wafer, and bond it to the wafer that contains the memory array, following an approach introduced in 3D NAND.
Toward a single and thermally stable platform optimized for peripheral transistors
The three groups of peripheral transistors come with their own requirements. The regular logic transistors must have good short channel control, high on current (Ion), and low off current (Ioff). With these characteristics, they closely resemble the logic transistors that are part of typical systems-on-chips (SoCs). They also need to enable multiple threshold voltages (Vth) to satisfy different design requirements.
The other two categories have more dissimilar characteristics and do not exist in typical logic SoCs. The analog sense amplifier requires good amplification, benefitting from a low threshold voltage (Vth). In addition, since signals are amplified, the mismatch between two neighboring sense amplifiers must be as low as possible. The ideal sense amplifier, therefore, is a very repeatable transistor with good analog functionality.
Finally, the row decoder is a digital transistor that needs an exceptionally thick gate oxide—compared to an advanced logic node—to sustain the higher bias. This makes the transistor inherently more reliable at the expense of being slower in operation.
Figure 2 Here are the main steps needed to fabricate a transistor for DRAM peripheral applications; the critical modules requiring specific developments are underlined. Source: PSS
In addition to these specific requirements, there are a number of constraints that apply to all peripheral transistors. One critical issue is the thermal stability. In current DRAM process flows with DRAM memory arrays sitting next to the periphery, peripheral transistors are fabricated before DRAM memory elements. The periphery is thus subjected to several thermal treatments imposed by the fabrication of the storage capacitor, access transistor, and memory back-end-of-line.
Peripheral transistors must, therefore, be able to withstand ‘DRAM memory anneal’ temperatures as high as 550-600°C for several hours. Next, the cost-effectiveness of DRAM chips must be preserved, driving the integration choices toward simpler process solutions than what logic flows are generally using.
To keep costs down, the memory industry also favors a single technology platform for various peripheral transistors—despite their individual needs. Additionally, there is a more aggressive requirement for low leakage and low power consumption, which benefits multiple DRAM use cases, especially mobile ones.
The combination of all these specifications makes a direct copy of the standard logic process flow impossible. It requires optimization of specific modules, including the transistors’ gate stack, source/drain junctions, and source/drain metal contacts.
Editor’s Note: This is first part of the article series about the latest advancements in DRAM designs. This part focuses on DRAM basics, peripheral circuits, and the journey toward a single, cost-effective, and thermally stable technology platform optimized for peripheral transistors. The second part will provide a detailed account of DRAM periphery advancements.
Alessio Spessot, technical account director, has been involved in developing advanced CMOS, DRAM, NAND, emerging memory array, and periphery during his stints at Micron, Numonyx, and STMicroelectronics.
Naoto Horiguchi, director of CMOS device technology at imec, has worked at Fujitsu and the University of California Santa Barbara while being involved in advanced CMOS device R&D.
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