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A previous design idea (DI), “Gated 555 astable hits the ground running” fixed the problem of the excessively long first pulse generated by 555 astables when gated by the RESET pin from oscillation-off to oscillation-on. See Figure 1 and Figure 2.
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Figure 1 The problem – first oscillation cycle has a too-long first pulse generated by 555 astables when gated by the RESET pin from oscillation-off to oscillation-on.
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Figure 2 The fix via C2 charge injection when Vreset = V+ to equalize pulse length.
However, unstated in the DI was the simplifying assumption that Vreset = V+ if the C2 = C1/2 fix is to work. But what if they’re not equal?
The LMC555 is rated for V+ supply voltages from 1.5 V to 15 V which lie outside the recommended limits of most logic families. This makes the ability to choose V+ unequal to Vreset a frequently useful thing. Happily, a C2 can still be chosen that will work with most combinations of supply rails. Specifically, the arithmetic is…
- Let Ct = total required timing capacitance.
- Then C2 = Ct * V+ / Vreset / 3
- C1 = Ct – C2
Some examples:
- Vreset = 5v and V+ = 1.5v, C2 = 0.1Ct, C1 = 0.9Ct
- Vreset = 3v and V+ = 5v, C2 = 0.2Ct, C1 = 0.8Ct
- Vreset = 5v and V+ = 5v, C2 = 0.33Ct, C1 = 0.67Ct
- Vreset = 5v and V+ = 15v, C2 = Ct, C1 = 0
Stephen Woodward’s relationship with EDN’s DI column goes back quite a long way. Over 100 submissions have been accepted since his first contribution back in 1974.
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