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The EDA trio—Cadence Design Systems, Siemens EDA, and Synopsys—is working hands in hand with TSMC to facilitate production-ready EDA tools for the mega-fab’s newest and most advanced processes. These EDA outfits showcased their IC design solutions at the TSMC 2024 North America Technology Symposium held in Santa Clara, California, on 24 April 2024.
The EDA tie-ups with TSMC show how toolmakers have established a symbiotic relationship with large fabs to support chip designers on advanced semiconductor manufacturing nodes. Moreover, it demonstrates why design flow migration is critical when chip designs move from one advanced node to the next.
- Cadence
Cadence showcased its node-to-node design migration flow based on the Cadence Virtuoso Studio, which facilitates the migration of schematic cells, parameters, pins, and wiring from one TSMC process node to another. Next, Virtuoso ADE Suite’s simulation and circuit optimization environment tunes and optimizes the new schematic to ensure the design achieves all required specifications and measurements.
That allows IC designers using Cadence tools on TSMC process nodes to automatically recognize and extract groups of devices in an existing layout and apply them to similar groups in the new layout. Cadence has also been working closely with TSMC to ensure its EDA tools’ compatibility with fab’s advanced nodes, including N3E and N2 process technologies.
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Figure 1 The enhanced PDKs and EDA methodologies simplify and accelerate the design migration from one process node to another. Source: Cadence
- Siemens EDA
Siemens EDA displayed its IC design solutions for TSMC’s latest process and advanced packaging technologies, including IC verification tool Calibre nmPlatform now certified for TSMC’s N2 process. At TSMC’s event, Siemens EDA also demonstrated its FastSPICE platform for circuit verification of nanometer analog, RF, mixed-signal, memory; it’s now certified for TSMC’s N3P, N2 and N2P process nodes.
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Figure 2 The EDA toolset certifications are crucial in migration to new IC manufacturing process and advanced packaging technologies. Source: Siemens EDA
Siemens EDA also provided details about collaboration with TSMC to certify its Calibre 3DSTACK solution’s support for the foundry’s latest 3Dblox standard. TSMC’s 3Dblox technology addresses specific IC test and diagnosis challenges that arise at 2-nm geometries and below.
- Synopsys
Synopsys also unveiled details about its latest collaborations with the Taiwanese fab, including a co-optimized photonic IC flow, which is integrated with the EDA firm’s 3DIC Compiler and supports TSMC’s 3Dblox technology.
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Figure 3 The production-ready design flows were showcased for TSMC’s advanced nodes at the symposium. Source: Synopsys
Additionally, Synopsys showcased its digital and analog design flows compatible with TSMC’s N3/N3P and N2 process nodes. The EDA toolmaker is also working closely with TSMC to ensure the design productivity and optimization of its AI-driven flows such as Synopsys DSO.ai.
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