JEDEC announced upcoming raw card designs for memory modules, which will complement two DDR5 clock driver standards published earlier this year. These raw card memory device standards are intended for use in client computing applications, such as laptops and desktop PCs, and will be supported by related appendix specifications.
Currently, JEDEC’s JC-45 Committee for DRAM Modules is developing the raw card designs in collaboration with the JC-40 Committee for Digital Logic and the JC-42 Committee for Solid-State Memories. The DDR5 clock driver standards include JESD323 (Clocked Unbuffered Dual Inline Memory Module) and JESD324 (Clocked Small Outline Dual Inline Memory Module).
Integrating a clock driver into a DDR5 DIMM improves memory stability and performance while enhancing signal integrity and reliability at high speeds. By locally regenerating the clock signal, the clock driver ensures stable operation at elevated clock rates. The initial version of the DDR5 clock driver enables data rates to increase from 6400 Mbps to 7200 Mbps, with future versions targeting up to 9200 Mbps.
According to JEDEC, member DIMM suppliers can provide advance solutions today, while non-members will gain access to design files once published. Available configurations include 1R×8, 1R×8 with EC4, 2R×8, 2R×8 with EC4, and 1R×16.
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