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Advanced packaging technology continues to make waves this year after being a prominent highlight in 2023 and is closely tied to the fortunes of a new semiconductor industry star: chiplets. IDTechEx’s new report titled “Advanced Semiconductor Packaging 2024-2034: Forecasts, Technologies, Applications” explores advanced packaging’s current landscape while going into detail about emerging technologies such as 2.5D and 3D packaging.
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Figure 1 2.5D and 3D packaging facilitate greater interconnection densities for chips serving applications like AI, data centers, and 5G. Source: IDTechEx
After fabs manufacture chips on silicon wafers through various advanced processes, packaging facilities receive completed wafers from fabs, cut them into individual chips, assemble or “package” them into final products, and test them for performance and quality. These packaged chips are then shipped to original equipment manufacturers (OEMs).
That’s part of the traditional semiconductor manufacturing value chain in which engineers build system-on-chips (SoCs) on silicon wafers and then move them to conventional packaging processes. Enter chiplets, manufactured of individual system modalities as standalone chips or chiplets on a wafer, then integrating these separate functionalities into a system through advanced packaging.
This premise brings advanced packaging to the forefront of semiconductor manufacturing innovation. In fact, the future of chiplets is intertwined with advancements in advanced packaging, where 2.5D and 3D technologies are rapidly taking shape to facilitate the commercial realization of chiplets.
2.5D and 3D packaging
While 1D and 2D semiconductor packaging technologies continue to dominate many applications, future advancements relate to 2.5D and 3D packaging to achieve the realization of more-than-Moore semiconductor realm. These technologies leverage wafer-level integration for miniaturization of components, leading to greater interconnection densities.
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Figure 2 Advanced packaging techniques like 2.5D and 3D improve system bandwidth and power efficiency by increasing I/O routing density and reducing I/O bump size. Source: Siemens EDA
2.5D technology, which facilitates larger packaging areas, mandates a shift from silicon interposers to silicon bridges or other alternatives such as high-density fan-out. But packaging components of different materials together also leads to many challenges. The IDTechEx report asserts that finding the right materials and manufacturing techniques is critical for 2.5D packaging adoption.
Next, 3D packaging brings new structures into play. That includes integrating one active die on top of another active die and reducing bump pitch distance. This 3D technique—called hybrid bonding—can be used for applications such as CMOS image sensors, 3D NAND flash and HBM memory, and chiplets. However, like 2.5 packaging, 3D packaging entails manufacturing and cost challenges as techniques like hybrid bonding demand new high-quality tools and materials.
OSAT and EDA traction
The development of an ecosystem often offers vital clues about the future of a nascent technology like advanced packaging. While challenges abound, recent semiconductor industry announcements bode well for IC packaging capabilities in the 2.5 and 3D eras.
Amkor, a major outsourced semiconductor assembly and test (OSAT) service provider, is investing approximately $2 billion to build an advanced packaging and test facility in Peoria, Arizona. The 55-acre site will be ready for production in a couple of years.
Then there is Silicon Box, an advanced panel-level packaging foundry focusing on chiplet integration, packaging, and testing. After setting up an advanced packaging facility in Singapore, the company is building a new site in Northen Italy to better serve fabs in Europe.
EDA toolmakers are also paying attention to this promising new landscape. For instance, Siemens EDA is working closely with South Korean OSAT nepes to expand its IC packaging capabilities for the 3D-IC era. Siemens EDA is providing nepes tools to tackle the broad range of complex thermal, mechanical, and other challenges associated with developing advanced 3D-IC packages.
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Figure 3 Innovator3D IC software delivers a fast, predictable path for the planning and heterogeneous integration of ASICs and chiplets using 2.5D and 3D packaging technologies. Source: Siemens EDA
Siemens EDA’s Innovator3D IC toolset shown above uses a hierarchical device planning approach to handle the massive complexity of advanced 2.5D/3D integrated designs with millions of pins. Here, designs are represented as geometrically partitioned regions with attributes controlling elaboration and implementation methods. That, in turn, allows critical updates to be quickly implemented while matching analytic techniques to specific regions, avoiding excessively long execution times.
Meanwhile, new materials and manufacturing processes will continue to be developed to confront the challenges facing 2.5D and 3D packaging. Perhaps another update before Christmas will provide greater clarity on where advanced packaging technology stands in 2024 and beyond.
Related Content
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- Intel and FMD’s Roadmap for 3D Heterogeneous Integration
- Heterogeneous Integration and the Evolution of IC Packaging
- Samsung’s advanced packaging pivot with Nvidia production win
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