While physical layer (PHY) interconnect IP has been making headlines after the emergence of the Universal Chiplet Interconnect Express (UCIe) specification, a Korean design house has announced the availability of controller IP that complies with the UCIe 1.1 standard.
The PHY part in UCIe encompasses link initialization, training, power management states, lane mapping, lane reversal, and scrambling. On the other hand, UCIe’s controller part includes the die-to-die adapter layer and the protocol layer.
Openedges Technology calls it OUC, and it derives its name from the term Openedges UCIe controller. Openedges, a supplier of memory subsystem IP, is based in Seoul, South Korea. Its controller IP extends on-chip AXI interconnections to multi-die connections to deliver multi-die connectivity across diverse applications.
The chiplet controller IP employs flits or flow control units for reliability and latency, thus preventing overflow at the receiver buffer. It also ensures seamless communication by synchronizing AXI parameters with its link partner, accommodating different AXI configurations through padding and cropping as per the default operation rules defined in AXI.
The highly configurable UCIe controller IP facilitates die-to-die interconnect and protocol connections. Source: Openedges Technology
In short, the new controller IP effortlessly integrates with the company’s on-chip interconnect IP. That synergy simplifies multi-chiplet interconnects while facilitating efficient bandwidth transfer capabilities.
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