Faraday’s MIPI D-PHY and V-by-One PHY IP portfolios are now compatible with UMC fabrication processes across nodes from 55 nm to 22 nm. The company’s video interface IP can be used in AIoT, industrial, consumer, and automotive applications, supporting both ASIC and IP business models.
The MIPI D-PHY IP on 22 nm offers a low operating voltage of 0.8 V, achieving a 12% reduction in power consumption and a 10% decrease in chip area compared to its 28-nm predecessor. It provides multiple transmit lanes with data rates ranging from 80 Mbps to 2.5 Gbps per lane. Additionally, the IP accommodates customizable combo I/O for various video receive interfaces and features flexible data and clock lane configurations.
Compatible with the V-by-One HS V1.4 and V1.5 standards for high-speed data transmission, Faraday’s V-by-One HS PHY IP on 22 nm handles data rates from 600 Mbps to 4 Gbps per lane. It cuts power consumption by 20% while operating at 0.8 V and decreases chip area by 30% compared to its 28-nm predecessor. The PHY IP also supports scrambling and clock data recovery.
Faraday’s fabless ASIC design services and silicon IP help customers streamline their R&D efforts and accelerate time-to-market.
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